Stack access control for memory device

ABSTRACT

An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

BACKGROUND

High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dies vertically and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).

For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance random access memory (DRAM) interface and vertically stacked DRAMs. FIG. 1A is a schematic diagram of a conventional HBM stack 11 including semiconductor chips, such as an I/F die (e.g. logic die) 12 and a plurality of core dies (DRAM dies) 13. The HBM stack 11 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 13 is coupled to two channels. In this example, the core dies 13 a, 13 b, 13 c and 13 d are coupled to channels A and C, channels B and D, channels E and G, and channels F and H, respectively. For example, a clock frequency, a command sequence, and data can be independently provided for each channel. FIG. 1B is a schematic diagram of a conventional HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The HBM stack 21 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 23 may include two channels. In this example, a stack group 24 a having a stack identifier (SID) “0” includes the core dies 23 a, 23 b, 23 c and 23 d including channels A and C, channels B and D, channels E and G, and channels F and H, respectively. A stack group 24 b having a stack ID (SID) “1” includes the core dies 23 e, 23 f, 23 g and 23 h including channels A and C, channels B and D, channels E and G, and channels F and H, respectively. Thus, a destination die among a plurality of core dies in each channel (e.g., core dies 23 a and 23 e of channel A) addressed in a command may be identified by the SID.

FIG. 2A is a wiring diagram of the conventional HBM stack 11 including the I/F die 12 and the plurality of core dies 13. The I/F die 12 of the HBM 11 stack provides interfaces 18 a, 18 b, 18 e and 18 f which provide signals on four input/output channels among the eight input/output channels, which function independently of each other. Memory arrays of the channel A, channel B, channel E and channel F of the core dies 13 a, 13 b, 13 c and 13 d may be coupled to the I/F die 12 via native input/output lines (IOs) 17 a, 17 b, 17 e and 17 f, respectively. For example, the native IOs 17 a to 17 f may be implemented as conductive vias. For example, the conductive vias may have a spiral structure. Each core die 13 may include a command circuit for each channel. For example, the core dies 13 a to 13 d may include command circuits 16 a to 16 d for channel A, channel B, channel E and channel F, respectively. Thus, clock signals, command signals and data signals for each channel may be transmitted independently and a plurality of data buses and their respective channels can operate individually.

FIG. 2B is a wiring diagram of the conventional HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The I/F die 22 of the HBM stack 21 provides interfaces 28 a, 28 b, 28 e and 28 f which provide signals on four input/output channels among the eight input/output channels of two stack groups. Memory arrays of channels A, B, E and F of the stack group 24 a and memory arrays of channels A, B, E and F of the stack group 24 b may be coupled to the same native input/output lines (IOs) 27 a, 27 b, 27 e and 27 f, respectively. For example, memory arrays of channel A of the core die 23 a in the stack group 24 a and memory arrays of channel A of the core die 23 e in the stack group 24 b may be coupled to the native IO 27 a. Each core die 23 may include a command circuit for each channel. For example, the core dies 23 a to 23 d in the stack group 24 a may include command circuits 26 a to 26 d for channel A, channel B, channel E and channel F, respectively. The core dies 23 e to 23 h in the stack group 24 b may include command circuits 26 e to 26 h for channel A, channel B, channel E and channel F, respectively. Each command circuit 26 may detect the SID in a command, check whether the SID in the command matches with an SID of the stack group of the core die 23 including the command circuit 26, and decode the command. If the SID matches, memory access actions responsive to the command may be performed. For example, when the interface 28 a transmits a command on the input/output line 27 a, the command circuit 26 a receives the command and check whether the SID in the command is “0”. The command circuit 26 a processes the command if the SID is “0” and ignores the command if the SID is “1”. The command circuit 26 e also receives the command and check whether the SID in the command is “1”. The command circuit 26 e processes the command if the SID is “1” and ignores the command if the SID is “0”. Thus, clock signals, command signals and data signals for each channel on each die may be transmitted independently.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a conventional HBM stack including the I/F die and the plurality of core dies.

FIG. 1B is a schematic diagram of a conventional HBM stacks including the I/F die and the plurality of core dies.

FIG. 2A is a wiring diagram of the conventional HBM stack including the I/F die and the plurality of core dies.

FIG. 2B is a wiring diagram of the conventional HBM stacks including the I/F die and the plurality of core dies.

FIG. 3 is a block diagram of an HBM stack in a semiconductor device in accordance with an embodiment of the present disclosure.

FIG. 4 is a timing diagram of command and data lines on the core dies of the HBM stack in accordance with an embodiment of the present disclosure.

FIG. 5 is a block diagram of an HBM stack in a semiconductor device in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG. 3 is a block diagram of an HBM stack 30 in a semiconductor device in accordance with an embodiment of the present disclosure. For example, the HBM stack 30 may include an interface (I/F) die 32 and a plurality of core dies (DRAM dies) CC0 to CC7. For example, the HBM stack 30 may include a command path, a data strobe path and a data path. In FIG. 3, a stack group 34 a includes four core dies (e.g., core chips) CC0 to CC3 including CC3 33 d which have an SID “0.” A stack group 34 b includes four core dies CC4 to CC7 including CC7 33 h which have an SID “1.” The I/F die 32 may include a command decoder 323 that may receive an intermediate IF command signal IF CMD from a controller (not shown) provided outside of the HBM stack 30, and may provide a plurality of command signals CMD. For example, the plurality of command signals CMD may include a plurality of row command/address signals R_0[5:0] and a plurality of column command/address signals C_0[7:0] to transmit commands. In a read operation, the I/F die 32 may also receive a data strobe signal DQS and data signals DQ[127:0] from the plurality of core dies CC0 to CC7 through a data strobe via 325 and a plurality of data vias 326, respectively. For example, the data strobe via 325 and the plurality of data vias 326 may be through silicon vias (TSV).

For example, the core die CC3 33 d may include a command circuit 333 d and a bypass circuit (e.g., a signal transmission circuit) 37 d. The command circuit 333 d may capture the plurality of command signals CMD including a command stack ID (CSID) indicative of a stack group, such as the stack group 34 a or the stack group 34 b (e.g., the SID being “0” or “1”), associated with a command (e.g., activate, read, write, precharge, etc.) in the plurality of command signals CMD. The bypass circuit 37 d may include a DSID FIFO circuit 334 d, which may capture the CSID responsive to each command and may further provide the captured CSID to a match circuit 336 d. The bypass circuit 37 d may also include a stack identifier (SID) circuit 335 d. The SID circuit 335 d may store a stack ID (SID) “0” of the core die CC3 33 d and provide an inverted signal of the stack ID to the match circuit 336 d. For example, the match circuit 336 d may be an AND circuit. The match circuit 336 d may receive the captured CSID from the DSID FIFO circuit 334 d and the inverted stack ID of the core die CC3 33 d to compare the captured SID in the command instructing “read” with the SID “0” indicative of the stack group 34 a and may provide a match signal that is active low (e.g. “0” or a logic low level for indicating the match). For example, if the CSID in the command is indicative of the stack group 34 b and the two SIDs do not match, the match circuit 336 d may provide an inactive match signal (e.g., “1” or a logic high level) to a data strobe multiplexer 337 d (e.g., a timing signal selector). The data strobe multiplexer 337 d may provide a data strobe signal DQS7 from the core die CC7 33 h as a data strobe signal DQS through a core data strobe via (TSV) 35 responsive to the inactive match signal from the match circuit 336 d. If the CSID in the command is indicative of the stack group 34 a and the two SIDs do match, the match circuit 336 d may provide an active match signal (e.g., “0” or a logic low level) to the data strobe multiplexer 337 d, and the data strobe multiplexer 337 d may provide a data strobe signal DQS3 from the core die CC3 33 d as the data strobe signal DQS responsive to the active match signal from the match circuit 336 d. Thus, either the data strobe signal DQS7 or the data strobe signal DQS3 may be provided as the data strobe signal DQS to the data strobe via 325 responsive to the CSID in the command.

The bypass circuit 37 d may include a data strobe enable circuit 338 d. For example, the data strobe enable circuit 338 d may provide the data strobe signal DQS7 from the core data strobe via 35 when the match signal from the match circuit 336 d is inactive (e.g., “1” or a logic high level). Thus, the data strobe signal DQS7 may be provided to a double data rate (DDR) moderator circuit 331 d. For example, the DDR moderator circuit 331 d may include flip-flops 3310 and 3311. The data strobe signal DQS7 from the data strobe enable circuit 338 d may enable either the flip-flop 3310 or the flip-flop 3311. For example, the flip-flop 3310 may latch data signals DT7 from a plurality of core data vias 36 responsive to a positive half period of the data strobe signal DQS7 (e.g., a first half period when the data strobe signal DQS7 is at a logic high level) and the flip-flop 3311 may latch the data signals DT7 from the plurality of core data vias 36 responsive to a negative half period of the data strobe signal DQS7 (e.g., a second half period when the data strobe signal DQS7 is at a logic low level). In this manner, a double data rate (DDR) transmission of the data signals DT7 may be executed at the timing of the data strobe signal DQS7, when the CSID is indicative of the stack group 34 b. For example, the core data strobe via 35 and the plurality of core data vias 36 may be through silicon vias (TSV).

The bypass circuit 37 d may include a data multiplexer circuit 332 d (e.g., a data signal selector). For example, the data multiplexer circuit 332 d may include a plurality of multiplexers 3320 and 3321 provided for data transmissions responsive to the positive half period and the negative half period of the data strobe signal DQS provided from the data strobe multiplexer 337 d respectively. For example, if the CSID in the command is indicative of the stack group 34 b and the two SIDs do not match, the plurality of multiplexers 3320 and 3321 in the data multiplexer circuit 332 d may provide the data signals DT7 from the core die CC7 33 h through the DDR moderator circuit 331 d responsive to the inactive match signal from the match circuit 336 d. If the CSID in the command is indicative of the stack group 34 a and the two SIDs do match, the plurality of multiplexers 3320 and 3321 in the data multiplexer circuit 332 d may provide data signals DT3 from the core die CC3 33 d through a read FIFO circuit 330 d responsive to the active match signal from the match circuit 336 d. For example, the read FIFO circuit 330 d may be coupled to a memory cell array 350 d to temporarily store data read out therefrom. The data signals from the plurality of multiplexers 3320 and 3321 may be provided to a data moderator 339 d. The data moderator 339 d may provide the data signals from the plurality of multiplexers 3320 and 3321 responsive to the positive half period and the negative half period of the data strobe signal DQS provided from the data strobe multiplexer 337 d respectively as data signals DQ[127:0]. Thus, either the data signals DT7 or the data signals DT3 may be provided as the data signals DQ[127:0] to the plurality of data vias 326 in a double data rate responsive to the CSID in the command.

For example, the core die CC7 33 h may include a command circuit 333 h and a bypass circuit 337 h. The command circuit 333 h may function similarly to the command circuit 333 d. However, the bypass circuit 37 h may function differently. For example, an SID circuit 335 h may provide SID “1” and a match circuit 336 h may provide an active match signal (e.g., “0” or a logic low level) constantly irrespective of the output of the DSID FIFO circuit 334 h. Responsive to the active match signal, the data strobe multiplexer 337 h may provide the data strobe signal DQS7 and the data multiplexer circuit 332 h may provide the data signals DT7 from the core die CC7 33 h through a read FIFO circuit 330 h responsive to the constantly active match signal. For example, the read FIFO circuit 330 h may be coupled to a memory cell array 350 h to temporarily store data read out therefrom.

FIG. 4 is a timing diagram of command and data lines on the core dies of the HBM stack 30 in accordance with an embodiment of the present disclosure. For example, a command (External CMD) “Read” transmitted in a clock cycle (=1tCK) may be received at an interface die (CMD Read@I/F) and forwarded to the core die CC3 33 d. The core die CC3 33 d may receive the command at time T0. If the core die CC3 33 d is selected, a data strobe signal DQS3 for the core die CC3 33 d may be activated at time T1, responsive to the command at time T0. Here, the data strobe signal DQS to be provided to the interface die may be based on the data strobe signal DQS3 from the core die CC3 33 d. On the other hand, if the core die CC7 33 h is selected, the core die CC3 33 d may forward the command to the core die CC7 33 h. The core die CC7 33 h may receive the command at time T2. If the core die CC7 33 h is selected, a data strobe signal DQS7 for the core die CC7 33 h may be activated at time T3, which is later than time T1, responsive to the command at time T2. Here, the data strobe signal DQS to be provided to the interface die may be based on the data strobe signal DQS7 from the core die CC7 33 h. Thus, the data signals may be read using the data strobe signal, either DQS3 or DQS7, that is produced by the same core die that stores and provides the data signals. Here, the data strobe signal DQS based on the data strobe signal DQS7 (DQS (DQS7 based) @CC3) and a first cycle of data signals from the core die CC7 33 h (FIFO in@CC3) have a time difference less than half the clock cycle (tCK), whereas the data strobe signal DQS based on the data strobe signal DQS3 ((DQS (DQS3 based) @CC3) and the first cycle of the data signals from the core die CC7 33 h (FIFO in@CC3) have a time difference longer than half the clock cycle, as shown in FIG. 4. Thus, using the data strobe signal DQS based on the data strobe signal DQS7 (DQS (DQS7 based) @CC3) for reading data from the core die CC7 33 h (FIFO in@CC3) may provide more accurate read timing than using the data strobe signal DQS based on the data strobe signal DQS3 ((DQS (DQS3 based) @CC3), as shown in FIG. 4.

FIG. 5 is a block diagram of an HBM stack 50 in a semiconductor device in accordance with an embodiment of the present disclosure. For example, the HBM stack 50 may include an interface (I/F) die 52 and a plurality of core dies CC0 to CC7. For example, the HBM stack 50 may include a command path, a data strobe path and a data path. In FIG. 5, a stack group 54 a includes four core dies (e.g., core chips) CC0 to CC3 including CC3 53 d which have an SID “0.” A stack group 54 b includes four core dies CC4 to CC7 including CC7 53 h which have an SID “1.” The I/F die 52 may include a command decoder 523 that may receive an intermediate IF command signal IF CMD, and may provide a plurality of command signals CMD. For example, the plurality of command signals CMD may include a plurality of row command/address signals R_0[5:0] and a plurality of column command/address signals C_0[7:0] to transmit commands. In a read operation, the I/F die 52 may also receive a data strobe signal DQS and data signals DQ[127:0] from the plurality of core dies CC0 to CC7 through a data strobe via 525 and a plurality of data vias 526, respectively. For example, the data strobe via 325 and the plurality of data vias 326 may be through silicon vias (TSV).

For example, the core die CC3 53 d may include a command circuit 533 d and a bypass circuit 57 d. The command circuit 533 d may capture the plurality of command signals CMD including a command stack ID (CSID) indicative a stack group, such as the stack group 54 a or the stack group 54 b (e.g., the SID being “0” or “1”), associated with a command (e.g., activate, read, write, precharge, etc.) in the plurality of command signals CMD. The bypass circuit 57 d may include a DSID FIFO circuit 534 d, which may capture the CSID responsive to the command and may further provide the captured CSID to a match circuit 536 d. The bypass circuit 57 d may also include a stack ID (SID) circuit 535 d. The SID circuit 535 d may store a stack ID (SID) “0” of the core die CC3 53 d and provide an inverted signal of the stack ID to the match circuit 536 d. For example, the match circuit 536 d may be an AND circuit. The match circuit 536 d may receive the captured CSID from the DSID FIFO circuit 534 d and the inverted stack ID of the core die CC3 53 d to compare the captured SID in the command instructing “read” with the SID “0” indicative of the stack group 54 a and may provide a match signal that is active low (e.g. “0” or a logic low level for indicating the match). For example, if the CSID in the command is indicative of the stack group 54 b and the two SIDs do not match, the match circuit 536 d may provide an inactive match signal (e.g., “1” or a logic high level) to a data strobe multiplexer 537 d, and the data strobe multiplexer 537 d may provide a data strobe signal DQS7 from the core die CC7 53 h as a data strobe signal DQS through a core data strobe via (TSV) 55 responsive to the inactive match signal from the match circuit 536 d. If the CSID in the command is indicative of the stack group 54 a and the two SIDs do match, the match circuit 536 d may provide an active match signal (e.g., “0” or a logic low level) to the data strobe multiplexer 537 d, and the data strobe multiplexer 537 d may provide a data strobe signal DQS3 from the core die CC3 53 d as the data strobe signal DQS responsive to the active match signal from the match circuit 536 d. Thus, either the data strobe signal DQS7 or the data strobe signal DQS3 may be provided as the data strobe signal DQS to the data strobe via 525 responsive to the CSID in the command.

The bypass circuit 57 d may include a data strobe enable circuit 538 d. For example, the data strobe enable circuit 538 d may provide the data strobe signal DQS7 from the core data strobe via 55 when the match signal from the match circuit 536 d is inactive (e.g., “1” or a logic high level). Thus, the data strobe signal DQS7 may be provided to a single data rate (SDR) moderator circuit 531 d. For example, the SDR moderator circuit 531 d may be a flip-flop. The data strobe signal DQS7 from the data strobe enable circuit 538 d may enable the SDR moderator circuit 531 d. For example, the SDR moderator circuit 531 d may latch data signals DT7 from a plurality of core data vias 56 responsive to a positive half period of the data strobe signal DQS7 (e.g., a first half period when the data strobe signal DQS7 is at a logic high level). In this manner, a single data rate (SDR) transmission of the data signals DT7 may be executed at the timing of the data strobe signal DQS7, when the CSID is indicative of the stack group 54 b. For example, the core data strobe via 55 and the plurality of core data vias 56 may be through silicon vias (TSV).

The bypass circuit 57 d may include a data multiplexer circuit 532 d. For example, the data multiplexer circuit 532 d may be a multiplexer provided for data transmission responsive to the positive half period of the data strobe signal DQS provided from the SDR moderator circuit 531 d. For example, if the CSID in the command is indicative of the stack group 54 b and the two SIDs do not match, the data multiplexer circuit 532 d may provide the data signals DT7 from the core die CC7 53 h through the SDR moderator circuit 531 d to a data moderator 539 d, responsive to the inactive match signal from the match circuit 536 d. If the CSID in the command is indicative of the stack group 54 a and the two SIDs do match, the data multiplexer circuit 532 d may provide data signals DT3 from the core die CC3 53 d through a read FIFO circuit 530 d to a data moderator 539 d, responsive to the active match signal from the match circuit 536 d. For example, the read FIFO circuit 530 d may be coupled to a memory cell array 550 d to temporarily store data read out therefrom. The data moderator 539 d may provide the data signals from the data multiplexer circuit 532 d responsive to the positive half period of the data strobe signal DQS provided from the data strobe multiplexer 537 d respectively as data signals DQ[127:0]. Thus, either the data signals DT7 or the data signals DT3 may be provided as the data signals DQ[127:0] to the plurality of data vias 526 in a single data rate responsive to the CSID in the command.

For example, the core die CC7 53 h may include a command circuit 533 h and a bypass circuit 57 h. The command circuit 533 h may function similarly to the command circuit 533 d. However, the bypass circuit 57 h may function differently. For example, an SID circuit 535 h may provide SID “1” and a match circuit 536 h may provide an active match signal (e.g., “0” or a logic low level) constantly. Responsive to the active match signal, the data strobe multiplexer 537 h may provide the data strobe signal DQS7 and the data multiplexer circuit 532 h may provide the data signals DT7 from the core die CC7 53 h through a read FIFO circuit 530 h responsive to the constantly active match signal. For example, the read FIFO circuit 530 h may be coupled to a memory cell array 550 h to temporarily store data read out therefrom.

Logic levels of signals and logic gate combinations used in the embodiments described the above are merely examples. However, in other embodiments, combinations of logic levels of signals and combinations of logic gates other than those specifically described in the present disclosure may be used without departing from the scope of the present disclosure.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above. 

What is claimed is:
 1. An apparatus comprising: a first semiconductor chip; a second semiconductor chip; a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip; a first stack group including the first semiconductor chip; and a second stack group including the second semiconductor chip, wherein the first semiconductor chip is configured to provide a first timing signal to the first via and further configured to provide first data to the plurality of second vias responsive to the first timing signal, and wherein the second semiconductor chip is configured to provide the first data responsive to the first timing signal when the first semiconductor chip is designated, wherein the second semiconductor chip is further configured to provide a second timing signal and further configured to provide second data responsive to the second timing signal when the second semiconductor chip is designated, wherein the second semiconductor chip comprises: a command circuit configured to receive a command signal and further configured to provide a command stack identifier associated with the command signal; and a signal transmission circuit configured to receive the first timing signal from the first via and the first data from the plurality of second vias and further configured to provide the first data responsive to the first timing signal, when the command stack identifier is indicative of the first stack group and to provide the second data responsive to the second timing signal, when the command stack identifier is indicative of the second stack group, and wherein the signal transmission circuit comprises: a timing signal selector circuit configured to receive the first timing signal and the second timing signal, and further configured to provide the first timing signal when the command stack identifier is indicative of the first stack group and to provide the second timing signal, when the command stack identifier is indicative of the second stack group; and a data signal selector circuit configured to receive the first data and the second data, and further configured to provide the first data when the command stack identifier is indicative of the first stack group and to provide the second data, when the command stack identifier is indicative of the second stack group.
 2. The apparatus of claim 1, wherein the signal transmission circuit further comprises: a stack identifier circuit configured to provide a chip stack identifier indicative of the second stack group; and a match circuit configured to receive the command stack identifier and the chip stack identifier and further configured to provide a match signal responsive to whether the command stack identifier is indicative of the chip stack identifier.
 3. The apparatus of claim 1, wherein the signal transmission circuit further comprises a signal data moderator circuit configured to provide the first data responsive to the first timing signal and the command stack identifier indicative of the first stack group.
 4. The apparatus of claim 3, wherein the first semiconductor chip is configured to provide the first data at a double data rate, and wherein the signal data moderator circuit is configured to latch the first data responsive to a first half period and a second half period of the first timing signal.
 5. A semiconductor device comprising: a memory array in a stack group associated with a first stack identifier; a command circuit configured to receive a command signal, to decode a command and an address on the command signal and further configured to provide a command stack identifier associated with the address; a set of external terminals configured to receive a first combination of signals including external data signals and an external timing signal; and a signal transmission circuit configured to receive the first combination of signals from the set of external terminals and further configured to receive a second combination of signals including internal data signals from the memory array and an internal timing signal, wherein the signal transmission circuit is configured to provide the first combination of signals if the command stack identifier is different from the first stack identifier and further configured to provide the second combination of signals if the command stack identifier is the first stack identifier.
 6. The semiconductor device of claim 5, wherein the signal transmission circuit comprises: a timing signal selector circuit configured to receive the external timing signal and the internal timing signal and further configured to provide either the external timing signal or the internal timing signal as an output timing signal, responsive to the command stack identifier; and a data signal selector circuit configured to receive the external data signals and the internal data signals and further configured to provide either the external data signals or the internal data signals responsive, at least in part, to the command stack identifier, wherein the data signal selector circuit is further configured to provide either the external data signals or the internal data signals as output data signals responsive, at least in part, to the external timing signal or the internal timing signal, respectively.
 7. The semiconductor device of claim 5, wherein the signal transmission circuit further comprises: a stack identifier circuit configured to provide the first stack identifier; and a match circuit configured to receive the command stack identifier and the first stack identifier and further configured to provide a match signal responsive to whether the command stack identifier is indicative of the first stack identifier.
 8. The semiconductor device of claim 7, wherein the signal transmission circuit further comprises: a timing enable circuit configured to receive the external timing signal and the match signal and configured to provide the external timing signal responsive to the match signal; and a signal data moderator circuit configured to receive the external data signals from a portion of the set of external terminals and to receive the external timing signal from the timing enable circuit, and further configured to provide the external data signals responsive to the external timing signal when the command stack identifier indicative of another stack group different from the stack group.
 9. The semiconductor device of claim 8, wherein the signal data moderator circuit comprises at least one flip-flop circuit configured to receive the external timing signal and at least one external data signal of the external data signals and further configured to provide the at least one external data signal responsive to the external timing signal.
 10. The semiconductor device of claim 8, wherein the set of external terminals is configured to provide the first data at a double data rate, and wherein the signal data moderator circuit is configured to latch the first data responsive to a first half period and a second half period of the first timing signal.
 11. The semiconductor device of claim 10, wherein the signal data moderator circuit comprises at least one pair of flip-flop circuits configured to receive the external timing signal and at least one external data signal of the external data signals, and wherein one flip-flop circuit of the at least one pair of flip-flop circuits is configured to latch the first data responsive to a first half period and the other flip-flop circuit of the at least one pair of flip-flop circuits is configured to latch the first data responsive to a second half period of the first timing signal.
 12. The semiconductor device of claim 10, wherein the signal transmission circuit further comprises a data moderator configured to provide the output data signals responsive to the positive half period and the negative half period of the output timing signal.
 13. A method of transmitting data from a first semiconductor chip in a first stack group associated with a first stack identifier, the method comprising: receiving a command signal; decoding a command on the command signal; providing a command stack identifier associated with the command; receiving a first combination of signals including external data signals and an external timing signal from a second semiconductor chip; receiving a second combination of signals including internal data signals from a memory array in the first semiconductor chip and an internal timing signal; providing the first combination of signals if the command stack identifier is different from the first stack identifier; and providing the second combination of signals if the command stack identifier is the first stack identifier.
 14. The method of claim 13, further comprising: receiving the external timing signal and the internal timing signal; and providing either the external timing signal or the internal timing signal responsive to the command stack identifier.
 15. The method of claim 13, further comprising: receiving the command stack identifier and the first stack identifier; and providing a match signal responsive to whether the command stack identifier is indicative of the first stack identifier.
 16. The method of claim 15, further comprising: receiving the external timing signal and the match signal; providing the external timing signal responsive to the match signal; receiving the external data signals and the external timing signal; and providing the external data signals responsive to the external timing signal when the command stack identifier indicative of another stack group different from the stack group.
 17. The method of claim 16, further comprising: latching the external data signals responsive to a first half period and a second half period of the external timing signal, wherein the external data signals are received at a double data rate.
 18. The method of claim 17, wherein the first semiconductor chip comprises at least one pair of flip-flop circuits configured to receive the external timing signal and at least one external data signal of the external data signals, and wherein latching the external data signals comprises: latching the external data signals responsive to the first half period of the external timing signal by one flip-flop circuit of the at least one pair of flip-flop circuits; and latching the external data signals responsive to the second half period of the external timing signal by the other flip-flop circuit of the at least one pair of flip-flop circuits. 